The present invention relates generally to address and data transition detection. This technique is commonly used to reduce power consumption, especially in Static Random Access Memory devices (SRAM).
Conventional transition detection circuits generally consist of an exclusive OR gate and multiple inverters (See FIG. 1 and 2 for circuit diagrams). One input terminal of the exclusive OR gate is connected directly to the input line. The other input terminal is connected to the output of a series of inverters connected together. This series of inverters is positioned between the input line and the second input terminal to the exclusive OR gate. When the address or data input changes, the exclusive-OR gate generates a pulse whose width equals the delay caused by the series of inverters (See FIG. 3 for the timing diagram of the circuit of the circuit diagram of FIG. 2, which was provided by the SPICE simulation program).
These conventional transition detection circuits have several disadvantages. In particular, the parameters of the transition boundaries of the pulse are inconsistent, as the pulse width is non-adjustable and the pulse is extremely sensitive to noise. The width of the pulse, the slope of the transitional boundaries of the pulse, and the circuit's immunity to noise ultimately affect the speed of the extended circuit.
Regarding the adjustable pulse width, the number of additional inverters in series can be changed to adjust the pulse width. These adjustments generally occur in multiples of two, in order to maintain the proper polarity. The total number of inverters is generally an odd number. (FIG. 1 and 2 demonstrates the variable lengths of these inverter chains. FIG. 1 has one inverter in series. FIG. 2 has nine inverters in series.) Regarding the transitional boundaries, the slope of the transitional boundaries is small, which slows down the operation of the entire system. Regarding the sensitivity of these traditional circuits to noise, changes in the IN signal translates to direct changes in the OUT signal. If the IN signal is noisy, the OUT signal is noisy as well. These traditional circuits tend to be extremely sensitive to noisy inputs (See FIG. 4 for a for the timing diagram for the circuit diagram presented in FIG. 2 for a noisy input signal, which is provided by the SPICE simulation of the circuit).